1. Field of the Invention
The present invention relates to discrete cosine transform calculation processors, employed in particular in real time compression systems for transmitting digital television picture signals over limited bandwidth links.
2. Description of the Prior Art
The use of digital coding and compression techniques for processing television picture signals to be transmitted without significant degradation over limited bandwidth links is already known. Certain of these techniques provide for real time processing of a television picture signal and yield satisfactory results both with regard to transmitted picture quality and the compression ratio obtained, using two-dimensional discrete cosine transform calculations. For the purposes of such calculations, the television picture signal is divided into successive matrix blocks of N.times.N non-overlapping digital picture elements. These blocks are converted into successive sets of the N.times.N two-dimensional discrete cosine transform coefficients which, quantified and coded, are then transmitted over the line. By applying the property of separating the discrete cosine transform into two dimensions, the calculation of these transforms reduces to one-dimensional discrete cosine transform calculations.
The discrete cosine transform of a sequence of N data points i (j) where j=0, . . . N-1 is a sequence of N transformed data points I(k) where k=0, . . . N-1, also called coefficients, which are expressed by the equation: ##EQU1##
The discrete cosine transform calculation for a sequence of N data points is carried out by executing a time sequence of real operations in the form of an algorithm. One of these algorithms, usable for N=2n where n is equal to 2 or more and of the type known as a "butterfly" algorithm, is given in an article entitled "A Fast Computational Algorithm for the Discrete Cosine Transform" by Wen-Hsiung, Chen, C. Harrison-Smith and S. C. Fralick published in IEEE Transactions on Communications, September 1977. It breaks down the processing of the N data points of the sequence to be transformed to obtain the corresponding N coefficients, ignoring a normalization factor, into a limited number of successive stages each yielding N results. These steps consist in addition or subtraction operations carried out on appropriate pairs of data points from the sequence to be transformed or appropriate pairs of results from the step directly preceding that in question, and in multiplying the results of a step, preceding that in question, by a cosine or sine function followed by operations of addition or subtraction either on one of the results of these multiplications and one of the preceding step results or on two of the results of these multiplications, taken in suitable pairs in both cases.
A calculation processor implementing an algorithm deduced from the preceding algorithm, referred to as that of W. H. Chen et al, is published in the article "A High-Speed FDCT Processor for Real-Time Processing of NTSC Color TV Signal" by Ali Jalali and K. R. Rao in IEEE Transactions on Electromagnetic Compatibility, Vol EMC-24, No 2, May 1982. This processor, designed for processing sequences of picture elements of a television picture signal, is of modular structure operating overall in pipeline mode. It comprises three types of operator module assigned to three different sets of operations to be carried out during all stages of processing the picture elements of a sequence. One of these modules, called the simple module, has two inputs and is assigned to an addition/subtraction operation. A second module, called the composite module, has four inputs and is assigned to multiplying two of the inputs by a cosine/sine function and addition/subtraction of these products and to addition/subtraction of each of the other two inputs with one of these products. The third module, called the basic module, has two inputs and is assigned to multiplying each of the inputs by a cosine/sine function and to the addition/subtraction of these products. These various modules are under the control of a programmed store module providing for the simultaneous functioning of the various operator modules and the exploitation of the results which each of them produces by the next module or at the outputs of the last module.
The overall structure of a processor of this kind is complex, utilizing numerous addition/subtraction units and numerous multiplication units.
Another calculation processor implementing an algorithm also derived from the algorithm of W. H. Chen et al published in IEEE Transactions on Communications and also designed for processing a television picture signal is described in American U.S. Pat. No. 4,302,775. The modified algorithm disclosed in this patent breaks down the set of calculations to be carried out on N picture elements into successive stages each producing N results. Thus for transforming 16 picture elements (N=16), the modified algorithm disclosed in this American patent recommends an organization of the set of calculations into five successive stages, the first assigned to operations of addition or subtraction on appropriate pairs of input picture elements, the second assigned to operations identical to that of the first stage but applying to appropriate pairs of results of said first stage, the third assigned to multiplying the preceding results by constants (defining cosine or sine values and able to take the values .+-.1) and addition or subtraction of pairs of the products obtained, the fourth assigned to operations of addition or subtraction on pairs of results of the third stage, and the fifth assigned to multiplying each of the preceding results by constants (defining values of a cosine or sine function) and addition of pairs of the products obtained.
The resulting processor thus comprises five sets of operator circuits disposed one after the other and assigned to the operations carried out according to the five successive processing stages as defined hereinabove. The processor as a whole is synchronized to the incoming timing rate of the input picture elements, but each set of operator circuits has its own control signals derived from the input picture element timing rate. This processor is of complex structure since it functions in pipeline mode.
An object of the present invention is to define a simplified architecture for a discrete cosine transform calculation processor for calculating the transform of a sequence of N digital data points, using a modified algorithm based on that of W. H. Chen et al which yields a compact and readily integrated final structure.